ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 53

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 29 shows the timing for sending data from the FPGA logic to the Core. In the input case, the constraints on
the data are specified in terms of setup and hold times on the data at the interface relative to the clock at the inter-
face. For correct operation these constraints must be met. In the case shown, launch and capture occur on the
same (rising) clock edge. Data is captured before the next data is launched, so there will be no hold margin prob-
lem. Launched data also has nearly a full clock period to become stable at the capture latch, so setup margin
should not be a problem.
Figure 29. Full Cycle, Align and Bypass Mode Input Configuration and Timing (-1 Speed Grade)
a.) Configuration
a.) Timing (ns)
Requirements on
RETIME_CLK
FPGA_CLK
FPGA_SYSCLK
FPGA_CLK
DINxx[7:0]
FPGA
Logic
setup time - 1.3
- 1.7
+
Primary Clock
Data Valid
Q
3.0 ns
0.0
1.0
3.0
Hold
hold time = 2.3
Δ t
Launch
Note: xx = [AA, AB, ..., BD]
4.7
FPGA_SYSCLK
5.7
DINxx[7:0]
7.7
53
9.4
10.4
12.4
Δ t
1.4 ns
Capture
14.1
15.1
D
17.1
ORCA ORT8850 Data Sheet
+
RETIME_CLK
Embedded
2.4 ns
Core
.