ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 27

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 8. Byte Ordering, Quad STS-12 (OC-48) Format
All internal framing is based on the system frame pulse (SYS_FP) which is a one-cycle pulse at an 8kHz rate.
There is one system frame pulse for all 8 channels or both quads. When the framer receives the system frame
pulse the individual overhead bytes are identified.
HSI Macrocell
The ORT8850 High-Speed Interface (HSI) provides a physical medium for high-speed asynchronous serial data
transfer between ASIC devices. The devices can be mounted on the same PC board or mounted on different
boards and connected through the shelf back-plane. The ORT8850 CDR macro is an eight-channel Clock-Phase
Select (CPS) and data retime function with serial-to-parallel demultiplexing for the incoming data stream and paral-
lel-to-serial multiplexing for outgoing data. The ORT8850 uses an eight-channel HSI macro cell. The HSI macro
consists of three functionally independent blocks: receiver, transmitter, and PLL synthesizer.
The PLL synthesizer block generates the necessary 850 MHz clock for operation from a 106.25 MHz, reference.
The PLL synthesizer block is a common asset shared by all eight receive and transmit channels. The PLL refer-
ence clock must match the interface frequency.
The HSI_RX block receives differential 850 Mbits/s serial data without clock at its LVDS receiver input. Based on
data transitions, the receiver selects an appropriate 850 MHz clock phase for each channel to retime the data. The
retimed data and clock are then passed to the deMUX (deserializer) module. DeMUX module performs serial-to-
parallel conversion and provides the 106 Mbits/s data and clock.
The HSI_TX block receives 106 Mbits/s parallel data at its input. MUX (serializer) module performs a parallel-to-
serial conversion using an 850 MHz clock provided by the PLL/synthesizer block. The resulting 850 Mbits/s serial
data stream is then transmitted through the LVDS driver.
The loopback feature built into the HSI macro provides looping of the transmitter data output into the receiver input
when desired.
All rate examples described here are the maximum rates possible. The actual HSI internal clock rate is determined
by the provided reference clock rate. For example, if a 77.76 MHz reference clock is provided, the HSI macro will
operate at 622 Mbits/s.
Transmit Path Logic
In the transmit direction each STM quad will receive frame aligned streams of STS-12 data (maximum of four
streams per quad) from the FPGA logic. The transmitter receives data interface in a parallel 8-bit format. A com-
mon frame pulse for all 8 channels is provided as an input from the FPGA logic to the transmit SONET block.
The system frame pulse is a single pulse at the reference clock rate every 9720 clock cycles. For a 77.76 MHz ref-
erence clock this creates an 8KHz pulse rate. The system frame pulse (SYS_FP) is used to generate the A1/A2 in
the transmit direction. It is also used by the Pointer Mover Block to perform the line side loopback, which otherwise
uses the LINE_FP frame pulse also provided by the user from the FPGA to the Embeddded ASIC Block. The Func-
tion of the LINE_FP is mentioned in the Pointer Mover bypass description.
The system frame pulse is common to all channels in the transmit direction. Once it is received from the FPGA
logic, the data to be transmitted goes through the following processing steps:
• A parity check is performed on the data
• The Transport Overhead (TOH) data is modified (optional)
STS-12 C -->
STS-12 D -->
STS-12 A -->
STS-12 B -->
12
24
36
48
21
33
45
9
18
30
42
6
15
27
39
3
11
23
35
47
27
20
32
44
8
17
29
41
5
14
26
38
2
ORCA ORT8850 Data Sheet
10
22
34
46
19
31
43
7
16
28
40
4
13
25
37
1