ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 48

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 15. FPGA/Embedded Core Interface Signals (Continued)
SYS_FP
LINE_FP
TOH_CLK
Signals to TX Logic Blocks
DINxx[7:0]
DINxx_PAR
Signals from RX Logic Blocks
DOUTxx[7:0]
DOUTxx_PAR
DOUTxx_FP
DOUTxx_SPE
DOUTxx_C1J1
DOUTxx_EN
CDR_CLK_xx
Signals to TOH Logic Blocks (Note: These signals are active only in the serial TOH insertion mode)
TX_TOH_CK_EN
TOH_INxx
Signals from TOH Logic Blocks (Note: These signals are active only in the serial TOH insertion mode)
RX_TOH_CK_EN
RX_TOH_FP
TOH_CK_FP_EN
TOH_OUTxx
FPGA/Embedded Core
Interface Signal Name
xx=[AA,…,BD]
ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks
Input (I) to or Output (O)
from Core
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
System frame pulse generated inside the FPGA logic. This is a sin-
gle clock pulse of FPGA_SYSCLK every 9720 clock cycles. For a
77.76 MHz reference clock the system frame pulse is at the SONET
standard of 8 KHz. All the eight Transmit channels' first A1 byte
should be aligned to the SYS_FP. Internally SYS_FP is used when
Far end loopback (line side loopback) needs to be performed. This
loopback can only be performed when Pointer Mover is not
bypassed.
User-provided frame pulse used by only the Pointer Mover block in
the receive direction. The Pointer Mover moves the data to align it
with the LINE_FP. If the Pointer Mover is bypassed, LINE_FP is not
used.
Clock driven from the FPGA to clock the TOH processor. This clock
can be in the range from 25MHz to 77.76MHz. If not using the TOH
communication channel this signal can be connected to GND.
Byte wide data for channel xx. This data is ultimately preset on the
serial LVDS pin TXDxx_W_[P:N] (work) and TXDxx_P_[P:N] (pro-
tect).
Parity input for byte wide data DINxx. Odd or even parity selection
is controlled by a bit in the control register at 0x3000C.
Byte wide data for channel AA
Parity output for byte wide data DOUTxx[7:0]. Odd/Even is con-
trolled by control register at 0x3000C.
Frame pulse output from the SONET framer. A single clock pulse to
indicate the start of the SONET frame. If bypassing the pointer
mover/interpreter this pulse will line up directly with the first A1 on
DOUTxx[7:0]. If using the pointer interpreter/mover DOUTxx_FP
will fall several clock cycles before the A1 on DOUTxx[7:0] due to
the latency from the pointer mover.
When '1' indicates SPE bytes are on the DOUTxx[7:0] lines. Only
available when using the pointer interpreter/mover
When '1' indicates the C1J1 bytes are on the DOUTxx[7:0] lines.
Only available when using the pointer interpreter/mover.
Indicates the state of register setting for DOUTxx_EN.
Recovered clock from the Channel xx SERDES. If not using the
alignment FIFO all of the parallel data from Channel xx will be
clocked from this clock.
Active-hi TOH_CLK enable. If using serial TOH insertion this enable
must be active.
Serial TOH insertion port for channel xx.
When '1' indicates a control register bit has been set to enable the
TOH clock and frame pulse.
Single clock frame pulse to indicate the serial link frame pulse.
When '1' indicates the TOH serial link clock is enabled.
TOH serial link output from Channel xx
48
Signal Description
ORCA ORT8850 Data Sheet