ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 55

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 31 shows the timing for sending TOH data from the FPGA logic to the Core. As in the earlier input example,
the constraints on the data are specified in terms of setup and hold times on the data at the interface relative to the
clock at the interface. In the case shown, launch and capture occur on different clock edges (rising edge in the
FPGA). Data is captured before the next data is launched, so there will be no hold margin problem. Launched data
also has nearly a full clock period to become stable at the capture latch, so setup margin should not be a problem
for the timing relationships assumed in the example. Actual timing analysis should be performed for each applica-
tion because of the wide range of possible skew values.
Figure 31. Half Cycle, TOH Input Configuration and Timing (-1 Speed Grade)
ASB_IN_TOH_CLK
a. Configuration
b. Timing (ns)
Requirements on
TOH_CLK
FPGA_CLK
FPGA_CLK
FPGA
Logic
TOH_INxx
+2.0 ns assumed
Secondary Clock
±3.0 ns skew
+
setup time = 0.0
Q
0.0
1.8
2.0
Δ t
Note: xx = [AA, AB, ..., BD]
Launch
4.7
Valid
Data
6.5
TOH_CLK
6.7
TOH_INxx
Capture
hold time = 1.8
55
Hold
9.4
11.2
11.4
Δ t
1.8 ns
14.1
D
15.9
16.1
ORCA ORT8850 Data Sheet
-
ASB_IN_TOH_CLK
Embedded
Core