ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 25

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Backplane Transceiver Core Detailed Description
SONET Logic Blocks, Detailed Description
The following sections describe the data processing performed in the SONET logic blocks. A 622 Mbits/s is
assumed in the descriptions however, as noted in the Overview sections, the ORT8850 can operate at variable
rates up to 850 Mbits/s. At a top level, the descriptions are separated into processing in the transmit path (FPGA to
serial link) and processing in the receive path (serial link to FPGA). A top level drawing of the two data paths and
associated clocks is shown in Figure 11. The various processing options are selected by setting bits in control reg-
isters and status information is written to status registers. Both types of registers can be written and/or read from
the System Bus or the MicroProcessor Interface (MPI). Memory maps and descriptions for the registers are given
in Table 19.
Figure 11. ORT8850 Top Level Data Flow
Table 5. Channel Alignment, Transparent TOH (Continued)
Initial Register Settings
0x30038
0x30050
0x30068
0x30080
0x30098
0x300B0
0x300C8
Transmit (TX)
Receive (RX)
Register
Address
FPGA_SYSCLK
Path
Path
DOUTxx[7:0]
DINxx[7:0]
FPGA
Logic
8 - bit
8 - bit
0x07
0x07
0x07
0x07
0x07
0x07
0x07
8-bit
Value
PFU
PFU
Channel AB in functional mode without AIS-L
Channel AC in functional mode without AIS-L
Channel AD in functional mode without AIS-L
Channel BA in functional mode without AIS-L
Channel BB in functional mode without AIS-L
Channel BC in functional mode without AIS-L
Channel BD in functional mode without AIS-L
register bit
Pointer
Mover /
Interpreter
-FPGA_SYSCLK or CDR_CLK_xx
-FPGA_SYSCLK if alignment FIFO is used
-Per channel CDR_CLK_xx if alignment FIFO is not used
register bits
25
Embedded
Core
Alignment
SONET
FIFO
8 -bit
8 -bit
bypass
Description
8 - bit
8 - bit
8 - bit
SONET
bypass
register bits
ORCA ORT8850 Data Sheet
8-bit
SERDES
SERDES
PLL
RX Serial Data
I/O MUX, I/O DEMUX
TX Serial Data
And LVDS Buffers
System
Clock
1 - bit
1 - bit
-