HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 634
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
If a transition is made to sleep mode when all modules are stopped (MSTPCR = H'FFFF), or
modules other than the 8-bit timers are stopped (MSTPCR = H'EFFF), operation of the bus
controller and I/O ports is also halted, enabling current dissipation to be further reduced.
Table 19.3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register
MSTPCRH
MSTPCRL
Note: Bits 15, 11, 8, 7, and 4 to 0 can be read or written to, but do not affect operation.
19.5.2
DTC Module Stop: Depending on the operating status of the DTC, the MSTP14 bit may not be
set to 1. Setting of the DTC module stop mode should be carried out only when the respective
module is not activated.
For details, refer to section 7, Data Transfer Controller (DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
624
Usage Notes
Bit
MSTP15
MSTP14
MSTP13
MSTP12
MSTP11
MSTP10
MSTP9
MSTP8
MSTP7
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
Module
—
Data transfer controller (DTC)
16-bit timer pulse unit (TPU)
8-bit timer
—
D/A converter
A/D converter
—
—
Serial communication interface (SCI) channel 1
Serial communication interface (SCI) channel 0
—
—
—
—
—
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