HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 9

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

4.3
4.4
4.5
4.6
4.7
Section 5
5.1
5.2
5.3
5.4
5.5
5.6
Section 6
6.1
4.2.5
Traces ................................................................................................................................ 97
Interrupts............................................................................................................................ 98
Trap Instruction .................................................................................................................
Stack Status after Exception Handling .............................................................................. 100
Notes on Use of the Stack.................................................................................................. 101
Overview............................................................................................................................ 103
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions......................................................................................................... 106
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources................................................................................................................ 111
5.3.1
5.3.2
5.3.3
Interrupt Operation ............................................................................................................ 116
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ....................................................................................................................... 126
5.5.1
5.5.2
5.5.3
5.5.4
DTC Activation by Interrupt ............................................................................................. 128
5.6.1
5.6.2
5.6.3
Overview............................................................................................................................ 131
6.1.1
6.1.2
State of On-Chip Supporting Modules after Reset Release .................................
Interrupt Controller
Features ................................................................................................................ 103
Block Diagram...................................................................................................... 104
Pin Configuration ................................................................................................. 105
Register Configuration ......................................................................................... 105
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 107
IRQ Enable Register (IER) .................................................................................. 108
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 109
IRQ Status Register (ISR) .................................................................................... 110
External Interrupts................................................................................................ 111
Internal Interrupts ................................................................................................. 112
Interrupt Exception Handling Vector Table ......................................................... 112
Interrupt Control Modes and Interrupt Operation ................................................ 116
Interrupt Control Mode 0...................................................................................... 119
Interrupt Control Mode 2...................................................................................... 121
Interrupt Exception Handling Sequence .............................................................. 123
Interrupt Response Times..................................................................................... 125
Contention between Interrupt Generation and Disabling..................................... 126
Instructions that Disable Interrupts ...................................................................... 127
Times when Interrupts are Disabled..................................................................... 127
Interrupts during Execution of EEPMOV Instruction.......................................... 127
Overview .............................................................................................................. 128
Block Diagram...................................................................................................... 128
Operation .............................................................................................................. 129
Bus Controller
Features ................................................................................................................ 131
Block Diagram...................................................................................................... 132
System Control Register (SYSCR) ..................................................................... 106
.................................................................................................. 131
........................................................................................ 103
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