HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 844

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
The method for writing to TCSR is different from that for general registers to prevent inadvertent overwriting.
For details see section 11.2.4, Notes on Register Access.
Note: * Can only be written with 0 for flag clearing.
:
:
:
Overflow Flag
R/(W)*
OVF
0
1
7
0
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows from H'FF to H'00 in interval timer mode
Timer Mode Select
WT/IT
R/W
0
1
6
0
Interval timer mode: Sends the CPU an interval timer interrupt request
(WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF signal when
TCNT overflows
Timer Enable
TME
R/W
0
1
5
0
TCNT is initialized to H'00 and halted
TCNT counts
—
—
4
1
Note: *
CKS2 CKS1 CKS0
Clock Select
—
—
3
1
0
1
H'FFBC (W) H'FFBC (R)
The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
0
1
0
1
CKS2
R/W
2
0
0
1
0
1
0
1
0
1
ø/2 (initial value)
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
CKS1
R/W
Clock
1
0
CKS0
R/W
0
0
(when ø = 20 MHz)
25.6 s
819.2 s
1.6ms
6.6ms
26.2ms
104.9ms
419.4ms
1.68s
Overflow period*
WDT
835