HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 850

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
:
:
:
CCLR2
R/W
7
0
Counter Clear
Notes: 1. Synchronous operation setting is performed by setting the
0
1
CCLR1
R/W
0
1
0
1
6
0
2. When TGRC or TGRD is used as a buffer register, TCNT is
0
1
0
1
0
1
0
1
SYNC bit in TSYR to 1.
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture*
TCNT cleared by TGRD compare match/input capture*
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
CCLR0
R/W
5
0
CKEG1
Clock Edge
R/W
0
1
4
0
0
1
*
CKEG0
R/W
Count at rising edge
Count at falling edge
Count at both edges
3
0
Time Prescaler
0
1
H'FFD0
0
1
0
1
TPSC2
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
*: Don’t care
TPSC1
R/W
1
0
1
2
2
1
TPSC0
R/W
0
0
TPU0
841