PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 168

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
8.2
The interrupt controller is responsible for pre-
processing Interrupt Requests (IRQ) from a number of
on-chip peripherals and presenting them in the
appropriate order to the processor.
Figure 8-2 depicts the process within the interrupt con-
troller module. The interrupt controller is designed to
receive up to 96 IRQs from the processor core and
from on-chip peripherals capable of generating inter-
rupts. All IRQs are sampled on the rising edge of the
SYSCLK and latched in associated IFSx registers. A
pending IRQ is indicated by the flag bit being equal to
‘1’ in an IFSx register. The pending IRQ will not cause
further processing if the corresponding bit in the Inter-
rupt Enable (IECx) register is clear. The IECx bits act to
gate the interrupt flag. If the interrupt is enabled, all
IRQs are encoded into a 5-bit wide vector number. The
5-bit vector results in 0 to 63 unique interrupt vector
numbers. Since there are more IRQs than available
vector numbers, some IRQs share common vector
numbers. Each vector number is assigned an interrupt
priority level and shadow set number. The priority level
is determined by the IPCx register setting of the asso-
ciated vector. In Multi-Vector mode, all priority level 7
interrupts use a dedicated register set, while in Single
Vector mode, all interrupts may receive a dedicated
shadow set. The interrupt controller selects the highest
priority IRQ among all pending IRQs and presents the
associated vector number, priority level and shadow
set number to the processor core.
The processor core samples the presented vector
information between the ‘E’ and ‘M’ stage of the pipe-
line. If the vector’s priority level presented to the core is
greater than the current priority indicated by the CPU
Interrupt Priority bits IPLx (Status<15:10>), the inter-
rupt is serviced; otherwise, it will remain pending until
the current priority is less than the interrupt’s priority.
When servicing an interrupt, the processor core pushes
the program counter into the Exception Program
Counter (EPC) register in the CPU and sets Exception
Level bit EXL (Status<1>) in the CPU. The EXL bit dis-
ables further interrupts until the application explicitly re-
enables them by clearing the EXL bit. Next, it branches
to the vector address calculated from the presented
vector number.
DS61143A-page 166
Operation
Advance Information
The INTSTAT register contains the Interrupt Vector
Number bits, VEC (INTSTAT<5:0>), and Requested
Interrupt Priority bits, RIPLx (INTSTAT<10:8>), of the
current pending interrupt. This may not be the same as
the interrupt which caused the core to diverge from
normal execution.
The processor returns to the previous state when the
ERET (Exception Return) instruction is executed. ERET
clears the EXL bit, restores the program counter and
reverts the current shadow set to the previous one.
The PIC32MX Family interrupt controller can be config-
ured to operate in one of two modes:
• Single Vector mode – all interrupt requests will be
• Multi-Vector mode – interrupt requests will be
serviced at one vector address (mode out of
Reset).
serviced at the calculated vector address.
Notes: While the user can, during run time,
reconfigure the interrupt controller from
Single Vector to Multi-Vector mode (or
vice versa), such action is strongly dis-
couraged. Changing interrupt controller
modes after initialization may result in
undefined behavior.
The M4K core supports several different
interrupt processing modes. The interrupt
controller is designed to work in External
Interrupt Controller mode.
© 2007 Microchip Technology Inc.