PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 327

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 12-11: CHANGE NOTICE PIN AND
12.2.10
The Change Notice module is enabled as a source of
interrupts via the respective CN interrupt enable bits:
• CNIE (IEC1<0>)
• CNIF (IFS1<0>)
The interrupt priority level bits and interrupt subpriority
level bits must also be configured:
• CNIP<2:0> (IPC6<20:18>)
• CNIS<1:0> (IPC6<17:16>)
To enable CN interrupts, the ON bit (CNCON<15>)
must = 1, one or more CN input pins must be enabled
and the Change Notice Interrupt Enable bit, CNIE,
must = 1.
© 2008 Microchip Technology Inc.
Change
Notice
CN10
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
CN21
CN11
CN0
CN1
CN2
CN3
CN4
CN5
CN6
CN7
CN8
CN9
CNPUE10
CNPUE11
CNPUE12
CNPUE13
CNPUE14
CNPUE15
CNPUE16
CNPUE17
CNPUE18
CNPUE19
CNPUE20
CNPUE21
CNPUE0
CNPUE1
CNPUE2
CNPUE3
CNPUE4
CNPUE5
CNPUE6
CNPUE7
CNPUE8
CNPUE9
CHANGE NOTICE INTERRUPTS
Pull-Up
Weak
PULL-UP TABLE
Port Pin
RC14
RC13
RD13
RD14
RD15
RB15
RG6
RG7
RG8
RG9
RD4
RD5
RD6
RD7
RB0
RB1
RB2
RB3
RB4
RB5
RF4
RF5
Device
64-Pin
48
47
16
15
14
13
12
11
30
52
53
54
55
31
32
—
—
—
4
5
6
8
Pin#
Advance Information
100-Pin
Device
74
73
25
24
23
22
21
20
10
11
12
14
44
81
82
83
84
49
50
80
47
48
To prevent possible spurious interrupts when configur-
ing change notice interrupts, the following steps are
recommended:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The port must be read first to clear the mismatch con-
dition, then the CN interrupt flag, CNIF (IFS1<0>), can
be cleared in software. Failing to read the port before
attempting to clear the CNIF bit may not allow the CNIF
bit to be cleared.
In addition to enabling the CN interrupt, an Interrupt
Service Routine (ISR), is required. Example 12-1 and
Example 12-2 show a partial code example of an ISR.
Note:
Disable CPU interrupts.
Set desired CN I/O pin as input by setting corre-
sponding TRISx register bits = 1.
Note: If the I/O pin is shared with an analog
peripheral, it may be necessary to set the corre-
sponding AD1PCFG bit = 1 to ensure that the
I/O pin is a digital input.
Enable change notice module
ON (CNCON<15>) = 1.
Enable individual CN input pin(s); enable
optional pull-up(s).
Read corresponding PORT registers to clear
mismatch condition on CN input pins.
Configure the CN interrupt priority, CNIP<2:0>,
and subpriority CNIS<1:0>.
Clear CN interrupt flag, CNIF = 0.
Enable CN interrupt enable, CNIE = 1.
Enable CPU interrupts.
PIC32MX FAMILY
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143B - page 325