PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 286

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
11.25.3.1
The buffer descriptor is used in the following formats:
• Control
• Status.
Buffer descriptor control format, in which software
writes the descriptor and hands it to hardware, is
shown in Figure 11-3.
FIGURE 11-3:
DS61143B-page 284
63
31
bit 57-48 BYTE_COUNT<9:0>: Byte Count bits
bit 39
bit 38
bit 37
bit 36
bit 35
bit 34
bit 31-0
Note 1:
2:
3:
—
UOWN: USB Own bit
1 = USB module owns the BD and its corresponding buffer
0 = CPU owns the BD and its corresponding buffer
DATA0/1: Data Toggle Packet bit
1 = Transmit a Data 1 packet or Check received PID = DATA1, if DTS = 1
0 = Transmit a Data 0 packet or Check received PID = DATA1, if DTS = 1
KEEP: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set
0 = USB will hand back the BD once a token has been processed
NINC: DMA Address Increment Disable bit
1 = DMA address increment disabled
0 = DMA address increment enabled
DTS: Data Toggle Synchronization Enable bit
1 = Data Toggle Synchronization is enabled – data packets with incorrect sync value will be ignored
0 = No Data Toggle Synchronization is performed
BSTALL: Buffer Stall Enable bit
1 = Buffer STALL enabled
0 = Buffer STALL disabled
BUFFER_ADDRESS: Buffer Address bits
Starting point address of the endpoint packet data buffer.
This bit can be programmed by either the CPU or the USB module, and it must be initialized by the user to
the desired value prior to enabling the USB module.
Expected value of DATA PID (DATA0/DATA1) specified in the DATA0/1 field.
The individual buffer addresses in the BDT must be physical memory addresses.
Buffer Descriptor Format
Byte count represents the number of bytes to be transmitted or the maximum number of bytes to be
received during a transfer.
CPU must not modify the BD or the buffer.
USB module ignores all other fields in the BD.
U1STAT FIFO will not be updated and TRNIF bit will not be set at the end of each transaction.
STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit
remains set, BD value is unchanged).
Corresponding EPSTALL bit will get set on any STALL handshake.
58 57
USB BUFFER DESCRIPTOR FORMAT: SOFTWARE -> HARDWARE
BYTE COUNT<9:0>
(1)
Advance Information
BUFFER ADDRESS<31:0>
(3)
48 47
(2)
Buffer descriptor status format, in which hardware
writes the descriptor and hands it back to software, is
shown in Figure 11-4.
—
40 39 38 37 36 35 34 33 32
© 2008 Microchip Technology Inc.
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