PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 237

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

EXAMPLE 10-4:
© 2008 Microchip Technology Inc.
/*
The following code example illustrates a DMA channel 0 configuration for the normal addressing
mode transfer with pattern match enabled. DMA channel 0 transfer from the UART1 to a RAM buffer
while DMA channel 1 transfers data from the RAM buffer to UART2. Transferred strings are at most
256 characters long. Transfer on UART2 will start as soon as the UART1 transfer is completed.
*/
IEC1CLR=0x00010000;
IFS1CLR=0x00010000;
DMACONSET=0x00008000;
DCH0CON=0x3;
DCH1CON=0x62;
DCH0ECON=(27 <<8)| 0x30;
DCH1ECON=(42 <<8)| 0x30;
DCH0DAT=DCH1DAT=’\r’;
DCH0SSA=VirtToPhys(&U1RXREG); // transfer source physical address
DCH0DSA=VirtToPhys(myBuff); // transfer destination physical address
DCH0SSIZ=1;
DCH0DSIZ=0;
DCH0CSIZ=1;
DCH1SSA=VirtToPhys(myBuff); // transfer source physical address
DCH1DSA=VirtToPhys(&U2TXREG); // transfer destination physical address
DCH1SSIZ=0;
DCH1DSIZ=0;
DCH1CSIZ=1;
DCH0INTCLR=0x00ff00ff;
DCH1INTCLR=0x00ff00ff;
DCH1INTSET=0x00090000;
IPC9CLR=0x00001f1f;
IPC9SET=0x00000b16;
IEC1SET=0x00020000;
DCH0CONSET=0x80;
// do something else
// the UART1 RX interrupts will initiate the DMA channel 0 transfer
// once this transfer is complete, the DMA channel 1 will start
// upon DMA channel 1 transfer completion will get an interrupt
while(!intCh1Ocurred);
unsigned char myBuff<256>;// transfer buffer
CONFIGURING THE DMA FOR CHAINING MODE OPERATION
// disable DMA channel 0 interrupts
// clear any existing DMA channel 0 interrupt flag
// enable the DMA controller
// channel 0 off, priority 3, normal mode, no chaining
// channel 1 off, priority 2, normal mode,
// chain to higher priority
// (ch
// start irq is UART1 RX, pattern enabled
// start irq is UART1 TX, pattern enabled
// pattern value, carriage return
// program channel 0 transfer
// source size is 1 byte
// dst size at most 256 bytes
// one byte per UART transfer request
// program channel 1 transfer
// source size at most 256 bytes
// dst size is 1 byte
// one byte per UART transfer request
// DMA0: clear events, disable interrupts
// DMA1: clear events, disable interrupts
// DMA1: enable Block Complete and error interrupts
// clear the DMA channels 0 and 1 priority and
// subpriority
// set IPL 5, subpriority 2 for DMA channel 0
// set IPL 2, subpriority 3 for DMA channel 1
// enable DMA channel 1 interrupt
// turn channel on
// poll DMA channel 1 interrupt
Advance Information
0), enable events detection while disabled
PIC32MX FAMILY
DS61143B-page 235