PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 185

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 9-3:
© 2008 Microchip Technology Inc.
bit 31
bit 23
bit 15
bit 7
Legend:
R = Readable bit
U = Unimplemented bit
bit 31
bit 30-24
bit 23-4
bit 3
bit 2
bit 1
bit 0
Note 1: The TAG and Status of the Line pointed to by CHEIDX (CHEACC<3:0>).
LTAGBOOT
R/W-0
R/W-x
R/W-x
R/W-x
LTAGBOOT: Line TAG Address Boot
1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
Unimplemented: Read as ‘0’
LTAG<23:4>: Line TAG Address bits
LTAG bits are compared against physical address <23:4> to determine a hit. Because its address
range and position of Flash in kernel space and user space, the LTAG Flash address is identical for
virtual addresses, (system) physical addresses, and Flash physical addresses.
LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
Reserved:
R/W-x
R/W-x
R/W-x
U-0
—
CHETAG
LTAG<7:4>
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
(1)
R/W-x
R/W-x
R/W-x
: CACHE TAG REGISTER
U-0
—
Advance Information
R/W-x
R/W-x
R/W-x
U-0
—
LTAG<23:16>
LTAG<15:8>
P = Programmable bit
LVALID
R/W-0
R/W-x
R/W-x
U-0
—
PIC32MX FAMILY
LLOCK
R/W-x
R/W-x
R/W-0
U-0
—
r = Reserved bit
LTYPE
R/W-1
R/W-x
R/W-x
U-0
—
DS61143B-page 183
R/W-x
R/W-x
U-0
r-0
—
—
bit 24
bit 16
bit 8
bit 0