PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 44

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
2.4
The PIC32MX core offers a number of power
management features, including low-power design,
active power management, and power-down modes of
operation. The core is a static design that supports
slowing or halting the clocks, which reduces system
power consumption during idle periods.
2.4.1
The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see 23.0 “Power
Saving”.
2.4.2
The majority of the power consumed by the PIC32MX
core is in the clock tree and clocking registers. The
PIC32MX uses extensive use of local gated-clocks to
reduce this dynamic power consumption.
2.5
The PIC32MX core provides for an Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard
user mode and kernel modes of operation, the
PIC32MX core provides a Debug mode that is entered
after a debug exception (derived from a hardware
breakpoint, single-step exception, etc.) is taken and
continues until a debug exception return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the PIC32MX core.
In addition to the standard JTAG instructions, special
instructions defined in the EJTAG specification define
what registers are selected and how they are used.
DS61143B-page 42
Power Management
EJTAG Debug Support
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
LOCAL CLOCK GATING
Advance Information
2.5.1
Three debug registers (DEBUG, DEPC, and DESAVE)
have been added to the MIPS Coprocessor 0 (CP0)
register set. The DEBUG register shows the cause of
the debug exception and is used for setting up single-
step operations. The DEPC, or Debug Exception
Program Counter, register holds the address on which
the debug exception was taken. This is used to resume
program execution after the debug operation finishes.
Finally, the DESAVE, or Debug Exception Save,
register enables the saving of general purpose
registers used during execution of the debug exception
handler.
To exit debug mode, a Debug Exception Return
(DERET) instruction is executed. When this instruction
is executed, the system exits debug mode, allowing
normal execution of application and system code to
resume.
2.5.2
There
breakpoints defined in the EJTAG specification. These
stop the normal operation of the MCU and force the
system into debug mode. There are two types of simple
hardware breakpoints implemented in the PIC32MX
core: Instruction breakpoints and Data breakpoints.
The PIC32MX core has two data and six instruction
breakpoints
Instruction
operations, and the break is set on the virtual address.
A mask can be applied to the virtual address to set
breakpoints on a range of instructions.
Data breakpoints occur on load/store transactions.
Breakpoints are set on virtual address values, similar to
the Instruction breakpoint. Data breakpoints can be set
on a load, a store, or both. Data breakpoints can also
be set based on the value of the load/store operation.
Finally, masks can be applied to both the virtual
address and the load/store value.
2.5.3
The PIC32MX core includes Trace support for real-time
tracing of instruction addresses. The trace information
is collected in an off-chip memory, for post-capture
processing by trace regeneration software.
Off-chip trace memory is accessed through a special
trace probe that consists of 4 data pins plus a clock.
are
DEBUG REGISTERS
EJTAG HARDWARE BREAKPOINTS
INSTRUCTION TRACING
breaks
several
occur
types
© 2008 Microchip Technology Inc.
on
of
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instruction
hardware
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