PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 232

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
10.4
The mode is enabled by setting the CHXM bit
(DCHxCON<3>)
Extended Addressing mode transfer features:
• The maximum transfer size per channel is
• The source and destination sizes are concate-
• The Source and Destination Pointers
• Cell size is identical to block size. DCHxCSIZ and
10.4.1
The following steps are recommended to be taken to
configure a DMA transfer in Extended Addressing
mode:
• Disable the DMA channel interrupts in the INT
• Clear any existing channel interrupt flags in the
• Enable the DMA controller (if not already
• Set Channel Control register: Priority,
DS61143B-page 230
64 Kbytes.
nated and the size is 16 bits wide. DCHxSSIZ will
comprise the Most Significant bits of the channel
transfer size, the Destination Size Register
(DCHxDSIZ) will make up the Least Significant
bits of the transfer size.
(DCHxSPTR/DCHxDPTR) are concatenated in
the same way as the source and destination
sizes. A read of the DCHxDPTR register will
return the full 16-bit Channel Transfer Pointer
(DCHxSPTR concatenated with DCHxDPTR). A
read of DCHxSPTR in this mode will return the
high-order bits of the Transfer pointer.
DCHxCPTR are not used.
controller.
INT controller
enabled) in DMACON register.
Auto-Enable mode, etc., in DCHxCON. Use
CHXM = 1 (DCHxCON<3>) for Extended
Addressing mode. Don’t enable the channel yet.
Extended Addressing Mode
EXTENDED ADDRESSING MODE
CONFIGURATION
Advance Information
• Set the channel event control: clear/set the events
• If using a pattern match, set the pattern in the
• Set the transfer source and destination physical
• Set the block transfer size (DCHxSSIZ and
• Clear any existing event flag in DCHxINT register.
• If using interrupts:
• Enable the selected DMA channel with CHEN
• If not using system events to start the DMA
• Until the DMA transfer is complete, you can do
• If you enabled block complete interrupt you’ll be
• Otherwise, you can poll the DMA channel to see if
Refer to Example 10-2.
starting and aborting the transfer. If needed, also
set the pattern match enable in DCHxECON.
DCHxDAT register.
addresses (DCHxSSA and DCHxDSA registers).
DCHxDSIZ).
- Set the conditions that will generate an inter-
- Set the DMA channel interrupt priority and
- Enable the DMA channel interrupt in the INT
(DCHxCON<7>).
transfer use CFORCE (DCHxECON<7>) to start
transfer.
some other processing.
notified in the ISR that the DMA transfer
completed.
the transfer is completed using, for example,
CHBCIF (DCHxINT<3>).
rupt in the DCHxINT register (at least error
interrupt enable and abort interrupt enable,
usually block complete interrupt).
subpriority in the INT controller.
controller.
© 2008 Microchip Technology Inc.