PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 93

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
The PIC32MX microcontrollers provides 4 GB of uni-
fied virtual memory address space.
regions including program, data memory, SFRs, and
Configuration registers reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory
can be made executable, allowing PIC32MX to execute
from data memory.
Key Features:
• 32-bit native data width
• Separate User and Kernel mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
• Simple memory mapping with Fixed Mapping
• Cacheable and non-cacheable address regions
© 2008 Microchip Technology Inc.
Note:
program space
runaway code.
Translation (FMT) unit
MEMORY ORGANIZATION
Reference Manual” (DS61132) for a
This data sheet summarizes the features of
the PIC32MX family of devices. It is not
intended to be a comprehensive reference
source. Refer to the “PIC32MX Family
detailed description of this peripheral.
All memory
Advance Information
6.1
The PIC32MX microcontrollers implement two address
spaces: Virtual and Physical. All hardware resources
such as program memory, data memory and peripher-
als are located at their respective physical addresses.
Virtual addresses are exclusively used by the CPU to
fetch and execute instructions as well as access
peripherals. Physical addresses are used by peripher-
als such as DMA and Flash controller that access
memory independently of CPU.
The entire 4 GB virtual address space is divided into
two primary regions – user and kernel space. The lower
2 GB of space forms the User mode segment, called
useg/kuseg. The upper 2 GB of virtual address space
forms the kernel-only space. The kernel space is
divided into four segments of 512 MB each: kseg 0,
kseg 1, kseg 2 and kseg 3. Only Kernel mode applica-
tions can access kernel space memory. The peripheral
registers are only visible through kernel space.
The Fixed Mapping Translation (FMT) unit translates
the memory segments into corresponding physical
address regions. A virtual memory segment may also
be cached, provided the cache module is available on
the device. Please note that the kseg 1 memory seg-
ment is not cacheable, while kseg 0 and useg/kuseg
are cacheable.
PIC32MX FAMILY
PIC32MX Memory Layout
DS61143B-page 91