PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 195

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3
The CHECON register controls the configurations
available for instruction and data caching of Program
Flash Memory.
In addition to normal instruction caching, the prefetch
cache has the ability to cache lines specifically for
Flash Memory data.
The CHECON.DCSZ field controls the number of lines
allocated to program data caching. Table 9-2 shows
the cache line relationship for values of DCSZ. The
data caching capability is for read only data such as
constants, parameters, table data, etc., that are not
modified.
EXAMPLE 9-1:
9.3.1
Each line in the cache can be locked to hold its con-
tents. A line is locked if both LVALID=1 and LLOCK=1.
If LVALID=0 and LLOCK=1, the prefetch module
issues a preload request (see below). Locking cache
lines may reduce the performance of general program
flow. However, if one or two functions calls consume a
significant percent of overall processing, locking their
address can provide improved performance.
Though any number of lines can be locked, the cache
works most efficiently when locking either 1 or 4 lines.
If locking 4 lines, choose lines whose line number
divide by 4 have the same quotient. This locks an
entire LRU group which benefits the LRU algorithm.
For example, lines 8, 9, A, and B each have a quotient
of 2 when divided by 4.
EXAMPLE 9-2:
© 2008 Microchip Technology Inc.
#define LOCKED_LINE_NUM 3
/* lock first line of func1() in cache */
CHEACC = (1<<31) | LOCKED_LINE_NUM;
tmp = (unsigned long)func1;
ltagboot = (tmp & 0x00c00000) ? 0 : 1; // 0x9fc????? or 0x9d0?????
CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid
/* Prefetch Cache Initialization */
tmp = _CP0_GET_CONFIG(); // read CONFIG register
tmp |= 1; // kseg0 cacheable
_CP0_SET_CONFIG(tmp); // write CONFIG register
CHECON = (1<<4) | 3; // 3 wait-states,
Prefetch Configuration
LINE LOCKING
EXAMPLE CODE: INITIALIZATION CODE FOR PREFETCH MODULE
EXAMPLE CODE: LOCKING A LINE IN PREFETCH MODULE
// Prefetching enabled for cached memory
Advance Information
TABLE 9-2:
The CHECON.PREFEN field controls predictive
prefetching, which allows the prefetch module to spec-
ulatively fetch the next 16-byte aligned set of instruc-
tions.
The prefetch module loads data into the data array only
on accesses to cacheable regions (CCA bits = 3).
If cache lines are manually filled, it is recommended
that the following sequence be used.
DCSZ<1:0>
1.
2.
3.
Choose a cache line to fill.
Set the Lock and Valid bits of the cache line
by writing to CHETAG.
Write to each word of the cache line by writ-
ing to CHEW0, CHEW1, CHEW2, and
CHEW3.
00
01
10
11
PIC32MX FAMILY
None
Cache Line Number 15
Cache Line Number 14 and 15
Cache Line Number 12 through 15
Lines Allocated to Program Data
PROGRAM DATA CACHE
DS61143B-page 193