PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 300

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
An OTG A-device or embedded host may repower the
V
OTG B-device may also request that the OTG A-device
repower the V
is the purpose of the SRP.
Prior to requesting a new session, the B-device must
first check that the previous session has definitely
ended. To do this, the B-device must check that:
1.
2.
The B-device will be notified of condition 1 by the
SESENDIF (U1OTGIR<2>) interrupt.
Software can use the LSTATEIF (U1OTGIR<5>) bit
and the 1 ms timer to identify condition 2.
The B-device may aid in achieving condition 1 by dis-
charging the V
may do this by setting VBUSDIS (U1OTGCON<0>).
The B-device then proceeds by pulsing the D+ data
line. Software should do this by setting DPPULUP
(U1OTGCON<7>). The data line should be held high
for 5-10 ms.
After these initial conditions are met, the B-device may
begin requesting the new session. It begins by pulsing
the V
VBUSCHG (U1OTGCON<1>).
When an A-device detects SRP signaling (either via the
ATTACHIF (U1IR<6>) interrupt or via the SESVDIF
(U1OTGIR<3>) interrupt), the A-device must restore
the
(U1OTGCON<3>).
The B-device should not monitor the state of the V
supply while performing V
wards, if the B-device does detect that the V
has been restored (via the SESVDIF (U1OTGIR<3>)
interrupt), it must reconnect to the USB link by pulling
up D+. The A-device must complete the SRP by
enabling V
11.33.1.6
An OTG application with a micro-AB receptacle must
support HNP. HNP allows an OTG B-device to tempo-
rarily become the USB host. The A-device must first
enable HNP in the B-device. HNP may only be initiated
at full-speed. Refer to the On-The-Go supplement for
more information regarding HNP.
DS61143B-page 298
BUS
Note:
V
Both D+ and D- have been low for at least 2 ms.
BUS
supply at any time to initiate a new session. An
BUS
V
BUS
supply is below the session end voltage.
supply. Software should do this by setting
BUS
When the A-device powers down the V
supply, the B-device must disconnect its
pull-up resistor unless signalling a desire
to become host during HNP negotiation.
Refer to Section 11.33.1.6 “HNP”.
HNP
BUS
BUS
and driving reset signalling.
supply
supply to initiate a new session. This
supply through a resistor. Software
by
BUS
supply pulsing. After-
setting
BUS
Advance Information
VBUSON
supply
BUS
BUS
After being enabled for HNP by the A-device, the B-device
can request to become the host any time that the USB link is
in suspend state by simply indicating a disconnect. Software
may accomplish this by clearing the DPPULUP bit
(U1OTGCON<7>).
When the A-device detects the disconnect condition
(via the URSTIF (U1IR<0>) interrupt), the A-device
may allow the B-device to take over as host. The A-
device does this by signaling connect as a full-speed
device. Software may accomplish this by disabling host
operation, HOSTEN = 0 (U1CON<3>), and connecting
as a device (DPPULUP = 1). If the A-device instead
responds with resume signaling, the A-device will
remain as host.
When the B-device detects the connect condition (via
ATTACHIF (U1IR<6>), the B-device becomes host.
The B-device drives Reset signaling prior to using the
bus.
When the B-device has finished in its role as host, it
stops all bus activity and turns on its D+ pull-up resistor
by disabling host operations (HOSTEN = 0) and recon-
necting as a device (DPPULUP = 1).
Then the A-device detects a suspend condition (Idle for
3 ms), the A-device turns off its D+ pull-up. Alternatively
the A-device may also power-down the V
end the session.
When the A-device detects the connect condition (via
ATTACHIF), the A-device resumes host operation, and
drives Reset signaling.
11.33.2
For proper USB operation, the USB module must be
clocked with a 48 MHz clock. This clock source is used
to generate the timing for USB transfers; it is the clock
source for the SIE. The control registers are clocked at
the same speed as the CPU (refer to Figure 11-1).
The USB module clock is derived from the Primary
Oscillator (POSC) for USB operation. A USB PLL and
input prescalers are provided to allow 48 MHz clock
generation from a wide variety of input frequencies.
The USB PLL allows the CPU and the USB module to
operate at different frequencies while both use the
POSC as a clock source. To prevent buffer overruns
and timing issues, the CPU core must be clocked at a
minimum of 16 MHz.
The USB module can also use the on-board Fast RC
oscillator (FRC) as a clock source. When using this
clock source, the USB module will not meet the USB
timing requirements. The FRC clock source is intended
to allow the USB module to detect a USB wake-up and
report it to the interrupt controller when operating in
low-power modes. The USB module must be running
from the Primary oscillator before beginning USB
transmissions.
CLOCK REQUIREMENTS
© 2008 Microchip Technology Inc.
BUS
supply to