PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 437

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.12 UART Interrupts
The UART device has the ability to generate interrupts,
reflecting the events that occur during data communi-
cation. The following types of interrupts can be
generated:
• Receiver-data-available interrupts, signalled by
• Transmitter-buffer-empty interrupts, signalled by
• Receiver-buffer-overflow interrupt, signalled by
EXAMPLE 19-4:
EXAMPLE 19-5:
© 2008 Microchip Technology Inc.
/*
*/
U1RXIF (IFS0<27>), U2RXIF (IFS1<9>). This
event occurs when there is new data assembled
in the UxRXBUF receive buffer.
U1TXIF (IFS0<28>), U2TXIF (IFS1<10>). This
event occurs when there is space available in the
UxTXBUF transmit buffer and new data can be
written.
U1EIF (IFS0<26>), U2EIF (IFS1<8>). This event
occurs when there is an overflow condition for the
UxRXBUF receive buffer, i.e., new receive data
assembled but the previous one not read.
/*
*/
#pragma interupt Uart1IntHandler ipl4 vector 25
void Uart1IntHandler(void)
{
IFS0CLR = 0x1c000000;
}
The following code example illustrates a UART1 interrupt configuration.
When the UART1 interrupt is generated, the cpu will jump to the vector assigned to UART1
interrupt.
IEC0CLR=0x1c000000;
IFS0CLR=0x1c000000;
IPC6CLR=0x0000001f;
IPC6SET=0x000d;
IEC0SET=0x1c000000;
U1BRG
U1MODESET= 0x8000;
U1STASET= 0x1400;
The following code example demonstrates a simple interrupt service routine for UART1
interrupts. The user’s code at this vector should perform any application specific operations
and must clear the UART1 interrupt flags before exiting.
... perform application specific operations in response to the interrupt
= #BaudRate;
UART INITIALIZATION WITH INTERRUPTS ENABLE
UART1 ISR
Advance Information
// disable all UART1 interrupts
// clear any existing event
// clear the priority
// Set IPL=3, subpriority 1
// Enable Rx, Tx and Error interrupts
// Set Uart baud rate.
// Enable Uart for 8-bit Data, no Parity, and 1 Stop bit
// Enable Transmitter and Receiver
// Be sure to clear the UART1 interrupt flags
// before exiting the service routine.
A UART device is enabled as a source of interrupts via
the respective UART interrupt enable bits:
• U1RXIE (IEC0<27>) and U2RXIE (IEC1<9>)
• U1TXIE (IEC0<28>) and U2TXIE (IEC1<10>)
• U1EIE (IEC0<26>) and U2EIE (IEC1<8>)
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• U1IP (IPC6<4:2>), U1IS (IPC6<1:0>)
• U2IP (IPC8<4:2>), U2IS (IPC8<1:0>).
In addition to enabling the UART interrupts, an Interrupt
Service Routine (ISR) is required. Below is a partial
code example of an ISR.
Note:
PIC32MX FAMILY
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143B-page 435