PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
EXAMPLE 4-2:
4.2.6.4
If the device enters Sleep mode during a clock switch
operation, the clock switch operation is aborted. The
processor keeps the old clock selection and the
OSWEN bit (OSCCON<0>) is cleared. The WAIT
instruction is then executed normally.
4.2.6.5
The SOSC can be used by modules as well as the
CPU, therefore, the SOSC is controlled by a combina-
tion of software and hardware. Setting the SOSCEN bit
(OSCCON<1>) to a ‘1’ enables the SOSC. The SOSC
is disabled when it is not being used by the CPU mod-
ule and the SOSCEN bit is ‘0’. If the SOSC is being
TABLE 4-5:
DS61143B-page 78
Note 1:
Pin Name
SOSCO
SYSKEY = 0x12345678;
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;
OSCCONCLR = 111 << 16;
OSCCONSET = 101 << 16;
OSCCONSET = 1;
SYSKEY = 0x12345678;
SOSCI
OSCO
OSCO
OSCO
OSCO
OSCI
OSCI
N/A
N/A
N/A
N/A
During device start-up, the device oscillator configuration data is copied from device configuration to
COSC.
Entering Sleep Mode During a Clock
Switch
SOSC Control
FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC
FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC
FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC
FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC
CONFIGURATION OF PINS ASSOCIATED WITH THE OSCILLATOR MODULE
PERFORMING A CLOCK SWITCH
HS, HSPLL, XT, XTPLL
HS, HSPLL, XT, XTPLL
Clock Mode
EC, ECPLL
EC, ECPLL
EC, ECPLL
EC, ECPLL
SOSC
SOSC
Advance Information
// write invalid key to force lock
// Write Key1 to SYSKEY
// Write Key2 to SYSKEY
// OSCCON is now unlocked
// make the desired change
// This can be in ‘C’ or assembly
// clear the PLL multiplier bits
// set he new PLL multiplier value
// request clock switch
// Relock the SYSKEY
// Write any value other than Key1 or Key2
// OSCCON is relocked
COSC<2:0>, POSCMD<1:0>
Configuration Bit FIeld
COSC<2:0>, POSCMD,
COSC<2:0>, POSCMD,
COSC<2:0>, POSCMD,
used as SYSCLK, such as after a clock switch, it can-
not be disabled by writing to the SOSCEN bit. If the
SOSC is enabled by the SOSCEN bit, it will continue to
operate when the device is in SLEEP. To prevent inad-
vertent clock changes the OSCCON register is locked.
It must be unlocked prior to software enabling or
disabling the SOSC.
4.3
The pins used by the POSC and SOSC are shared by
other peripherals modules. Table shows the function of
these shared pins in the available oscillator modes.
When the pins are not used by a oscillator they are
available for use as general I/O pins or by use by a
peripheral sharing the pin. .
COSC<2:0>, POSCMD
COSC<2:0>, POSCMD
COSC<2:0>
COSC<2:0>
COSC<2:0>
COSC<2:0>
COSC<2:0>
COSC<2:0>
OSCOFNC
OSCOFNC
OSCOFNC
Input/Output Pins
(1)
© 2008 Microchip Technology Inc.
O
I
TRIS
NPUT
UTPUT
X
X
X
X
X
X
X
X
X
X
PBCLK O
Pin Type
C
O
LOCK
I
GPIO
GPIO
GPIO
GPIO
OSC
OSC
OSC
OSC
NPUT
UTPUT
I
N
UT