PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 41

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3.1
The PIC32MX core provides a simple Fixed Mapping
Translation (FMT) mechanism that is smaller and
simpler than a full Translation Lookaside Buffer (TLB)
found in other MIPS cores. Like a TLB, the FMT
performs virtual-to-physical address translation and
provides attributes for the different segments. Those
segments that are unmapped in a TLB implementation
(kseg0 and kseg1) are translated identically by the
FMT. Figure 2-3 shows how the FMT is implemented in
the PIC32MX core.
FIGURE 2-3:
In general, the FMT also determines the cacheability of
each segment. These attributes are controlled via bits
in the Config register. Table 2-4 shows the encoding for
the K23 (bits 30:28), KU (bits 27:25), and K0 (bits 2:0)
fields of the Config register. The PIC32MX core passes
these Config fields to the Prefetch Cache module to
determine cacheability of Program Memory Flash
accesses. Table 2-5 shows how the cacheability of the
virtual address segments is controlled by these fields.
TABLE 2-4:
© 2008 Microchip Technology Inc.
K23, KU, and K0
Config Register
Fields
2
3
FIXED MAPPING TRANSLATION
CACHE COHERENCY
ATTRIBUTES
ADDRESS TRANSLATION DURING MEMORY ACCESS
Cache Coherency Attribute
Instruction
Address
Calculator
Data
Address
Calculator
Cacheable
Uncached
Virtual
Address
Virtual
Address
Advance Information
FMT
Physical
Address
Physical
Address
PIC32MX FAMILY
SRAM
Interface
Instn
SRAM
Data
SRAM
DS61143B-page 39