PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 43

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When ERL = 1, useg and kuseg become unmapped
(virtual address is identical to the physical address) and
uncached. This behavior is the same as if there was a
TLB. This mapping is shown in Figure 2-5.
FIGURE 2-5:
2.3.2
The SRAM interface includes dual instruction and data
interfaces.
The dual interface enables independent connection to
instruction and data devices. It yields the highest
performance,
simultaneous I and D requests which are then serviced
in parallel.
The internal buses are connected to the Bus Matrix
unit, which is a switch fabric that provides this parallel
operation.
© 2008 Microchip Technology Inc.
DUAL INTERNAL BUS INTERFACES
since
0xE000_0000
0xC000_0000
0xA000_0000
0x8000_0000
0x0000_0000
PIC32MX CORE FMT MEMORY MAP (ERL =
the
Virtual Address
useg/kuseg
pipeline
kseg3
kseg2
kseg1
kseg0
can
Advance Information
generate
2.3.3
When the core is operating in MIPS16e mode,
instruction fetches only require 16 bits of data to be
returned. For improved efficiency, however, the core
will fetch 32 bits of instruction data whenever the
address is word-aligned. Thus for sequential MIPS16e
code, fetches only occur for every other instruction,
resulting in better performance and reduced system
power.
0xE000_0000
0xC000_0000
0x8000_0000
0x0000_0000
PIC32MX FAMILY
1
)
MIPS16E EXECUTION
Physical Address
reserved
useg/kuseg
kseg3
kseg2
kseg0/kseg1
DS61143B-page 41