PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 298

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
4.
5.
6.
7.
8.
9.
10. Initialize the current (EVEN or ODD) TX EP0 BD
DS61143B-page 296
Set the USB address of the target device in the
address register U1ADDR<6:0>. After a USB
bus Reset, the device USB address will be zero.
After enumeration, it must be set to another
value, between 1 and 127, by the host software.
Write the token register with a SETUP command
to Endpoint 0, the target device’s default control
pipe (U1TOK = 0xD0). This will initiate a SETUP
token on the bus followed by a data packet. The
device handshake will be returned in the PID
field of BD0STAT after the packets complete.
When the module updates BD0STAT, a transfer
done interrupt will be asserted (U1IR<TRNIF>).
This completes the setup stage of the setup
transfer as described in Chapter 9 of the USB
specification.
To initiate the data stage of the setup transaction
(for example, get the data for the GET DEVICE
DESCRIPTOR command), set up a buffer in
memory to store the received data.
Initialize the current (EVEN or ODD) RX or TX
(RX for IN, TX for OUT) EP0 BD to transfer the
data.
a)
b)
Write the Token register with the appropriate IN
or OUT token to Endpoint 0, the target device’s
default control pipe) for example, an IN token for
a GET
(U1TOK = 0x90). This will initiate an IN token on
the bus followed by a data packet from the
device to the host. When the data packet com-
pletes, the BD0STAT is written and a transfer
done interrupt will be asserted (U1IR<TRNIF>).
For control transfers with a single packet data
phase, this completes the data phase of the
setup transaction. If more data needs to be
transferred, return to step 8.
To initiate the status stage of the setup transac-
tion, set up a buffer in memory to receive or send
the zero length status phase data packet.
to transfer the status data.
a)
b)
Set the BD status (BD0STAT) UOWN bit to
‘1’, data toggle (DTS) to DATA1 and byte
count to the length of the data buffer.
Set the BD data buffer address (BD0ADR)
to the starting address of the data buffer if it
is not already initialized.
Set the BD status (BD0STAT) to 0x8000 –
UOWN bit to ‘1’, data toggle (DTS) to
DATA0 and byte count to ‘0’.
Set the BDT buffer address field to the start
address of the data buffer.
DEVICE
DESCRIPTOR command
Advance Information
11. Write the Token register with the appropriate IN
11.33 Data Transfer with a Target Device
Complete all of the following steps to discover and con-
figure a connected device.
1.
2.
3.
4.
5.
6.
Note:
Note:
or OUT token to Endpoint 0, the target device’s
default control pipe) for example, an OUT token
for a GET DEVICE DESCRIPTOR command
(U1TOK = 0x10). This will initiate a token on the
bus, followed by a zero length data packet from
the host to the device. When the data packet
completes, the BD is updated with the hand-
shake from the device, and a transfer done inter-
rupt will be asserted (U1IR<TRNIF>). This
completes the status phase of the setup trans-
action.
Write the EP0 Control register (U1EP0) to
enable transmit and receive transfers as appro-
priate with handshaking enabled (unless isoch-
ronous transfers are to be used). If the target
device is a low-speed device, also set the Low-
Speed Enable bit (U1EP0<LSPD>). If you want
the hardware to automatically retry indefinitely if
the target device asserts a NAK on the transfer,
clear the Retry Disable bit (U1EP0<RETRY-
DIS>).
Set up the current buffer descriptor (EVEN or
ODD) in the appropriate direction to transfer the
desired number of bytes.
Set the address of the target device in the
address register (U1ADDR<6:0>).
Write the Token register (U1TOK) with an IN or
OUT token as appropriate for the desired end-
point. This triggers the module’s transmit state
machines to begin transmitting the token and
the data.
Wait
(U1IR<TRNIF>). This will indicate that the BD
has been released back to the microprocessor
and the transfer has completed. If the retry dis-
able bit is set, the handshake (ACK, NAK,
STALL or ERROR (0xf)) will be returned in the
BD PID field. If a stall interrupt occurs, then the
pending packet must be dequeued and the error
condition in the target device cleared. If a detach
interrupt occurs (SE0 for more than 2.5 μs), then
the target has detached (U1IR<DETACHIF>).
Once
(U1IR<TRNIF>)
examined and the next data packet queued by
returning to step 2.
Some
respond to one transaction per frame.
Use of automatic indefinite retries can lead
to a deadlock condition if the device never
responds.
for
the
the
devices
transfer
occurs, the
© 2008 Microchip Technology Inc.
transfer
can
done
done
only
BD can
effectively
interrupt
interrupt
be