PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 238

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX FAMILY
10.8
The DMA module has one integrated CRC generation
module shared by all channels. The CRC module is a
highly configurable, 16-bit CRC generator. The CRC
module can be assigned to any available DMA chan-
nel by setting the CRCCH bits (DCRCCON<1:0>)
appropriately. The CRC is enabled by setting the
CRCEN bit (DCRCCON<7>).
The CRC generator will take 1 system clock to process
each byte of data read from the source. This implies
that if 32 bits of data are read from the source, the
CRC generation will take 4 system clocks to process
the data.
The CRC module modifies the behavior of the DMA
channel associated with the CRC module. The two
operating modes for a DMA channel associated with
the CRC module are:
• Background Mode: CRC is calculated in the
• Append Mode: Data read from the source is not
CRC Configurable resources:
• The terms of the polynomial can be programmed
• The length of the polynomial generator can be
• The CRC module can be assigned to any avail-
• The CRC is enabled by setting the CRCEN bit
• The CRC generator can be seeded by writing to
• The CRC can be read as it progresses by reading
• Data Order: As data is read from the source regis-
DS61143B-page 236
background, with normal DMA behavior
maintained.
written to the destination, but the CRC data is
accumulated in the CRC data register. The accu-
mulated CRC is written to the destination address
when a block transfer completes.
using the DCRCXOR<15:0> bits. Considering the
CRC polynomial: x
needed to define this polynomial. However, the
value to be written to the DCRCXOR register will
be 0b0001 0000 0010 0000, i.e., 0x1020.
Note:
programmed using the PLEN (DCRCCON<12:8>)
bits. For the above polynomial, the size will be 16.
The PLEN will be programmed with length -1, i.e.,
0x0F.
able DMA channel by setting the CRCCH bits
(DCRCCON<2:0>) appropriately.
(DCRCCON<7>).
the DCRCDATA register before enabling the
channel that will use the CRC module.
the DCRCDATA register at any time during the
CRC generation.
ter, the data is fed into the CRC generator MSB
first.
CRC Module Operation
The LSb and MSb do not have to be
specified, they are always set. The actual
value used for the polynomial generator
will be 0x11021.
16
+ x
12
+ x
5
+ 1, 17 bits are
Advance Information
10.9
The CRC Background mode is enabled by clearing
CRCAPP (DCRCCON<6>).
In this mode, the behavior of the DMA channel is
maintained with data read from the channel source
being passed to the CRC module and then written
back to the destination.
In the Background mode, the calculated CRC is left in
the DCRCDATA register at the end of the block
transfer.
This mode can be used to calculate a CRC as data is
moved from source to destination. A good example of
where this can be used is to calculate a CRC as data
is transmitted to or received from the UART module.
When the data transfer is complete the user can read
the calculated CRC and either append it to the
transmitted data or verify the received CRC data.
10.9.1
Microchip recommends taking the following steps to
configure a CRC calculation in Background mode:
• Seed the CRC generator by writing the initial seed
• Set the polynomial generator by writing to the
• Set the polynomial generator length by writing the
• Attach the CRC calculation to the desired DMA
• Use the Background mode by clearing the
• Enable the CRC calculation by setting the
• Once the DMA transfer begins, the CRC
• Once the DMA transfer ends, the CRC result will
Refer to Example 10-5..
to the DCRCDATA register.
DCRCXOR register.
PLEN (DCRCCON<12:8>).
channel performing the Normal/Extended
Addressing mode transfer by writing the CRCCH
(DCRCCON<2:0>).
CRCAPP (DCRCCON<6>) bit.
CRCEN (DCRCCON<7>).
calculation will begin as well.
be available by reading the DCRCDATA register.
Note:
CRC Background Mode
CRC BACKGROUND MODE
CONFIGURATION
The configuration steps specific for the
CRC configuration are shown. The DMA
transfer configuration is the same as
previously explained (see Section 10.2
“DMA Controller Operation”).
© 2008 Microchip Technology Inc.