PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 463

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.
2.
3.
4.
EXAMPLE 20-6:
20.4
The PMP module has the ability to generate the follow-
ing types of interrupts reflecting the events that occur
during data transfers.
Master mode:
• Interrupt on every read and write operation.
Legacy Slave mode:
• Interrupt on every read and write byte
Buffered Slave mode:
• Interrupt on every read and write byte
• Interrupt on read or write byte of Buffer 3
• Interrupt on every read and write byte
• Interrupt on read or write byte of Buffer 3
The PMP module is enabled as a source of interrupt
using the PMP interrupt enable bit:
• PMPIE (IEC1<2>).
The interrupt priority level and subpriority level bits
must also be configured:
• The PMP interrupt status flag, PMPIF (IFS1<2>)
© 2008 Microchip Technology Inc.
Addressable Slave mode:
IEC1CLR = 0x0004
PMCON = 0x0000
PMMODE = 0x0100
IPC7SET = 0x001C;
IPC7SET = 0x0003;
IFS1CLR
IEC1SET
PMCONSET = 0x8000;
(PMDOUT<31:24>)
(PMDOUT<31:24>), PMA<1:0> = 11
- PMPIP<2:0> (IPC7<4:2>)
- PMPIS<1:0> (IPC7<1:0>)
If interrupts are used, disable the PMP interrupt
by clearing the interrupt enable bit PMPIE
(IEC1<2>) = 0.
Stop and reset the PMP module by clearing the
control bit ON (PMCON<15>) = 0.
Configure the desired settings in the PMCON
and PMMODE control registers.
If interrupts are used:
PMP Interrupts
= 0x0004;
= 0x0004;
ADDRESSABLE PARALLEL SLAVE PORT INITIALIZATION
//Disable PMP int
//Stop and Configure
//Config PMMODE
//Priority level=7
//subpriority=3
//Same as...
//IPC7SET=0x001F
//Enable PMP module
//Clear PMP int flag
//Enable PMP int
Advance Information
5.
Below is a partial code example of an ISR.
is typically cleared by the user’s software in the
ISR.
Note:
a)
b)
c)
Enable the PMP slave port by setting control bit
ON = 1.
PIC32MX FAMILY
Clear interrupt flag bit PMPIF
(IFS1<2>) = 0.
Configure the PMP interrupt priority bits
PMPIP<2:0> (IPC7<4:2>) and interrupt sub
priority bits PMPIS (IPC7<1:0>.
Enable PSP interrupt by setting interrupt
enable bit PMPIE = 1.
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143B-page 461