PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 173

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.6
When the priority of a requested interrupt is greater
than the current CPU priority, the interrupt request is
taken and the CPU branches to the vector address
associated with the requested interrupt. Depending on
the priority of the interrupt, the prologue and epilogue
of the interrupt handler must perform certain tasks
before executing any useful code. The following
examples provide recommended prologues and
epilogues.
8.6.1
When the interrupt controller is configured in Single
Vector mode, all of the interrupt requests are serviced
at the same vector address. The interrupt handler
routine must generate a prologue and an epilogue to
properly configure, save and restore all of the core reg-
isters, along with General Purpose Registers. At a
worst case, all of the modifiable General Purpose Reg-
isters must be saved and restored by the prologue and
epilogue.
8.6.1.1
When entering the interrupt handler routine, the inter-
rupt controller must first save the current priority and
exception PC counter from Interrupt Priority bits, IPLx
(Status<15:10>), and the ErrorEPC register, respec-
tively, on the stack. (Status and ErrorEPC are CPU reg-
isters.) If the routine is presented a new register set, the
previous register set’s stack register must be copied to
the current set’s stack register. Then, the requested pri-
ority may be stored in the IPLx from the Requested
Interrupt Priority bits, RIPLx (Cause<15:10>), Excep-
tion Level bit, EXL, and Error Level bit, ERL, in the Sta-
tus register (Status<1> and Status<2>) are cleared and
the Master Interrupt Enable bit (Status<0>) is set.
Finally, the General Purpose Registers will be saved on
the stack. (The Cause and Status registers are located
in the CPU.)
© 2007 Microchip Technology Inc.
Interrupt Processing
INTERRUPT PROCESSING IN
SINGLE VECTOR MODE
Single Vector Mode Prologue
Advance Information
EXAMPLE 8-5:
8.6.1.2
After completing all useful code of the interrupt handler
routine, the original state of the Status and EPC regis-
ters, along with the General Purpose Registers saved
on the stack, must be restored.
rdpgpr sp, sp
mfc0
mfc0
srl
addiu
sw
mfc0
sw
ins
ins
mtc0
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
addu
// start interrupt handler code here
PIC32MX FAMILY
Single Vector Mode Epilogue
k0, Cause
k1, EPC
k0, k0, 0xa
sp, sp, -76
k1, 0(sp)
k1, Status
k1, 4(sp)
k1, k0, 10, 6
k1,zero, 1, 4
k1, Status
s8, 8(sp)
a0, 12(sp)
a1, 16(sp)
a2, 20(sp)
a3, 24(sp)
v0, 28(sp)
v1, 32(sp)
t0, 36(sp)
t1, 40(sp)
t2, 44(sp)
t3, 48(sp)
t4, 52(sp)
t5, 56(sp)
t6, 60(sp)
t7, 64(sp)
t8, 68(sp)
t9, 72(sp)
s8, sp, zero
SINGLE VECTOR
INTERRUPT HANDLER
PROLOGUE IN ASSEMBLY
CODE
DS61143A-page 171