AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 22

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.4.1
6.4.2
32059K–03/2011
Programming Model
Register File Configuration
Status Register Configuration
The AVR32UC register file is shown below.
Figure 6-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
page 22
code flags and the R, T, and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 6-4.
Application
Bit 31
Bit 31
SP_APP
INT0PC
INT1PC
FINTPC
SMPC
0
-
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LC
Bit 0
1
0
-
and
0
Supervisor
Bit 31
-
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Figure 6-5 on page
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
The AVR32UC Register File
The Status Register High Halfword
0
-
Bit 0
DM
0
INT0
Bit 31
SP_SYS
D
0
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
0
-
M2
0
INT1
Bit 31
SP_SYS
FINTPC
23. The lower word contains the C, Z, N, V, and Q condition
INT0PC
INT1PC
SMPC
R12
R11
R10
M1
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
0
Bit 0
M0
1
INT2
Bit 31
EM
1
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
I3M
0
SS_STATUS
Bit 0
SS_SP_SYS
SS_SP_APP
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
SS_RAR
SS_RSR
I2M
FE
0
INT3
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
I1M
SMPC
0
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
I0M
0
Bit 16
GM
Exception
Bit 31
1
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit name
Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Exception Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Bit 0
NMI
Bit 31
AT32UC3B
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Figure 6-4 on
Secure
Bit 31
SP_SEC
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
22