AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 382

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.2.11
32059K–03/2011
Management of control endpoints
•Special considerations for control endpoints
•STALL handshake and retry mechanism
•Overview
•Control write
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are
cleared. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the user requests a STALL and can return to the main task, waiting
for the next SETUP request.
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in
UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these
endpoints. When read, their value are always zero.
Control endpoints are managed using:
Figure 22-15 on page 383
ler will not necessarily send a NAK on the first IN token:
• The RXSTPI bit which is set when a new SETUP packet is received and which shall be
• The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared
• The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to
• If the user knows the exact number of descriptor bytes that must be read, it can then
• Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the
cleared by firmware to acknowledge the packet and to free the bank.
by firmware to acknowledge the packet and to free the bank.
accept a new IN packet and which shall be cleared by firmware to send the packet.
anticipate the status stage and send a zero-length packet after the next IN token.
bytes have been sent by the host and that the transaction is now in the status stage.
shows a control write transaction. During the status stage, the control-
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