AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 261

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.5
20.6
20.6.1
20.6.2
20.6.3
20.7
32059K–03/2011
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Clocks
Interrupts
Table 20-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SSC before disabling the clock, to avoid freezing the SSC in an undefined state.
The SSC interrupt request line is connected to the interrupt controller. Using the SSC interrupt
requires the interrupt controller to be programmed first.
This chapter contains the functional description of the following: SSC functional block, clock
management, data framing format, start, transmitter, receiver, and frame sync.
The receiver and the transmitter operate separately. However, they can work synchronously by
programming the receiver to use the transmit clock and/or to start a data transfer when transmis-
sion starts. Alternatively, this can be done by programming the transmitter to use the receive
clock and/or to start a data transfer when reception starts. The transmitter and the receiver can
be programmed to operate with the clock signals provided on either the TX_CLOCK or
RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maxi-
mum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two.
Pin Name
RX_FRAME_SYNC
RX_CLOCK
RX_DATA
TX_FRAME_SYNC
TX_CLOCK
TX_DATA
I/O Lines Description
Pin Description
Receiver Frame Synchro
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
Type
Input/Output
Input/Output
Input
Input/Output
Input/Output
Output
AT32UC3B
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