AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 278
AT32UC3B1128-AUT
Manufacturer Part Number
AT32UC3B1128-AUT
Description
IC MCU AVR32 128KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
28
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
6-chx10-bit
Number Of Timers
3
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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20.9.3
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Receive Period Divider Selection
• STTDLY: Receive Start Delay
• STOP: Receive Stop Selection
32059K–03/2011
31
23
15
7
-
This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods.
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.
Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be done in relation to Receive
Sync Data reception.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new
Compare 0.
Receive Clock Mode Register
CKG
30
22
14
6
-
RCMR
Read/Write
0x10
0x00000000
CKI
29
21
13
5
-
STOP
28
20
12
4
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
25
17
9
1
AT32UC3B
CKS
24
16
8
0
278
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