AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 399

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.4.2
22.7.4.3
32059K–03/2011
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
HSB Address
Control
Status
DMA Channel descriptor
Programming a chanel:
Figure 22-30. Example of DMA Chained List
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint
(IN or OUT).
Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need
to be programmed to set up wether single or multiple transfer is used.
The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric.
• Offset 0:
• Offset 4:
• Offset 8:
– The address must be aligned: 0xXXXX0
– DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR
– The address must be aligned: 0xXXXX4
– DMA Channel n HSB Address Register: DMAnADDR
– The address must be aligned: 0xXXXX8
– DMA Channel n Control Register: DMAnCONTROL
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
Next Descriptor Address
Transfer Descriptor
HSB Address
Control
AT32UC3B
NULL
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