AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 573

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.6.3
26.6.4
26.6.5
26.6.6
26.6.7
26.6.8
32059K–03/2011
Data Swapping
Peripheral DMA Controller
Construction
Equalization Filter
Interpolation Filter
Sigma-Delta Modulator
If one want to get coherence between the sign of the input data and the output voltage one can
use the DATAN signal or invert the sign of the input data by software.
When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the
Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1
fields to be swapped.
The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA
Controller can be programmed to automatically transfer samples to the Audio Bitstream DAC
Sample Data Register (SDR) when the Audio Bitstream DAC is ready for new samples. In this
case only the CR.EN bit needs to be set in the Audio Bitstream DAC module. This enables the
Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Sta-
tus Register (ISR) or using interrupts. See the Peripheral DMA Controller documentation for
details on how to setup Peripheral DMA transfers.
The Audio Bitstream DAC is constructed of two 3rd order Sigma-Delta D/A converter with an
oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter
(Comb4) before being applied to the Sigma-Delta Modulator. In order to compensate for the
pass band frequency response of the interpolation filter and flatten the overall frequency
response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total
frequency response of the Equalization FIR filter and the interpolation filter is given in
2 on page
pass filtered to remove high frequency noise inserted by the modulation process.
The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for
the pass band frequency response of the sinc interpolation filter. The equalization filter makes
the pass band response more flat and moves the -3dB corner a little higher.
The interpolation filter interpolates from f
Comb filter, and the basic building blocks of this filter is a comb part and an integrator part.
This part is a 3rdorder Sigma-Delta Modulator consisting of three differentiators (delta blocks),
three integrators (sigma blocks) and a one bit quantizer. The purpose of the integrators is to
shape the noise, so that the noise is reduced in the band of interest and increased at the higher
frequencies, where it can be filtered.
574. The digital output bitstreams from the Sigma-Delta Modulators should be low-
s
to 128f
s
. This filter is a 4thorder Cascaded Integrator-
AT32UC3B
Figure 26-
573