AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 259

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20. Synchronous Serial Controller (SSC)
20.1
20.2
32059K–03/2011
Features
Overview
Rev: 3.1.0.2
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The Synchronous Serial Controller (SSC) provides a synchronous communication link with
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver
and the transmitter interface with three signals:
The transfers can be programmed to start automatically or on different events detected on the
Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller chan-
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing
with low processor overhead to the following:
• the TX_DATA/RX_DATA signal for data
• the TX_CLOCK/RX_CLOCK signal for the clock
• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
Provides serial synchronous communication links used in audio and telecom applications
Independent receiver and transmitter, common clock divider
Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
Configurable frame sync and data length
Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
AT32UC3B
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