AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 506

IC MCU AVR32 128KB FLASH 48-TQFP

AT32UC3B1128-AUT

Manufacturer Part Number
AT32UC3B1128-AUT
Description
IC MCU AVR32 128KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3B1128-AUT

Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
28
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
6-chx10-bit
Number Of Timers
3
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B1128-AUT
Manufacturer:
Atmel
Quantity:
10 000
• ACPA: RA Compare Effect on TIOA
• WAVE
• WAVSEL: Waveform Selection
• ENETRG: External Event Trigger Enable
• EEVT: External Event Selection
Note:
• EEVTEDG: External Event Edge Selection
• CPCDIS: Counter Clock Disable with RC Compare
32059K–03/2011
EEVTEDG
WAVSEL
ACPA
EEVT
0
1
2
3
0
1
2
3
0
1
2
3
1: Waveform mode is enabled.
0: Waveform mode is disabled (Capture mode is enabled).
1: The external event resets the counter and starts the counter clock.
0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA
output.
0
1
2
3
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse-
1: Counter clock is disabled when counter reaches RC.
0: Counter clock is not disabled when counter reaches RC.
quently no IRQs.
Effect
UP mode without automatic trigger on RC Compare
UPDOWN mode without automatic trigger on RC Compare
UP mode with automatic trigger on RC Compare
UPDOWN mode with automatic trigger on RC Compare
Edge
none
rising edge
falling edge
each edge
Effect
none
set
clear
toggle
Signal selected as external event
TIOB
XC0
XC1
XC2
TIOB Direction
input
output
output
output
(1)
AT32UC3B
506

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