AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 448
AT32UC3B1128-AUT
Manufacturer Part Number
AT32UC3B1128-AUT
Description
IC MCU AVR32 128KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
28
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
6-chx10-bit
Number Of Timers
3
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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22.8.2.19
Register Name:
Access Type:
Offset:
Reset Value:
• CHBYTELENGTH: Channel Byte Length
• BURSTLOCKEN: Burst Lock Enable
• DESCLDIRQEN: Descriptor Loaded Interrupt Enable
• EOBUFFIRQEN: End of Buffer Interrupt Enable
• EOTIRQEN: End of USB Transfer Interrupt Enable
• DMAENDEN: End of DMA Buffer Output Enable
32059K–03/2011
BURSTLOCKEN
31
23
15
7
-
This field determines the total number of bytes to be transferred for this buffer.
The maximum channel transfer size 64kB is reached when this field is zero (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.
This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is
ignored.
1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.
0: The DMA never locks the HSB access.
1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system
bus.
0: The Descriptor Loaded interrupt is disabled.
1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.
0: The end of buffer interrupt is disabled.
1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.
0: The end of usb OUT data transfer interrupt is disabled.
Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the USB line to properly closed the usb
transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
Device DMA Channel n Control Register
DESCLDIRQEN
30
22
14
6
-
UDDMAnCONTROL, n in [1..6]
Read/Write
0x0318 + (n - 1) * 0x10
0x00000000
EOBUFFIRQEN
29
21
13
5
-
EOTIRQEN
CHBYTELENGTH[15:8]
CHBYTELENGTH[7:0]
28
20
12
4
-
DMAENDEN
27
19
11
3
-
BUFFCLOSE
INEN
26
18
10
2
-
LDNXTCH
DESCEN
25
17
9
1
-
AT32UC3B
CHEN
24
16
8
0
-
448
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