AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 398

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.4
22.7.4.1
32059K–03/2011
USB DMA Operation
Introduction
USB packets of any length may be transferred when required by the USBB. These transfers
always feature sequential addressing. These two characteristics mean that in case of high
USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length”
since the average access latency of HSB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of
a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1kbyte
boundary crossing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. This is because these memories row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other HSB masters
address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA
Channel n Control (UDDMAnCONTROL) register.
The USBB average throughput may be up to nearly 12 Mbit/s. Its average access latency
decreases as burst length increases due to the zero wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by four
compared to native byte access. If at least 0 wait-state word burst capability is also provided by
the other DMA HSB bus slaves, each of both DMA HSB busses need less than 1.1% bandwidth
allocation for full USB bandwidth usage at 33MHz, and less than 0.6% at 66MHz.
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