AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 223

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 19-6. Master Write with One Data Byte
Figure 19-7. Master Write with Multiple Data Byte
Figure 19-8. Master Write with One Byte Internal Address and Multiple Data Bytes
32059K–03/2011
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK in the status register if the slave does not acknowledge the byte. As
with the other status bits, an interrupt can be generated if enabled in the interrupt enable register
(IER). If the slave acknowledges the byte, the data written in the THR, is then shifted in the inter-
nal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new
write in the THR. When no more data is written into the THR, the master generates a stop condi-
tion to end the transfer. The end of the complete transfer is marked by the TXCOMP bit set to
one. See
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
W
Write THR (DATA)
S
W
A
Figure
DADR
IADR(7:0)
A
19-6,
Write THR (Data n+1)
DATA n
Figure
W
A
19-7, and
A
DATA n
Write THR (Data n+1)
A
DATA
Figure 19-8 on page
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
Write THR (Data n+x)
STOP sent automaticaly
DATA n+5
Last data sent
P
A
223.
A
DATA n+x
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
AT32UC3B
A
A
P
P
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