AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 85

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.5
11.6
Table 11-1.
32059K–03/2011
Offset
0x00
0x04
Functional Description
User Interface
WDT Register Memory Map
The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This
also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field
(PSEL) in the CTRL register selects the watchdog time-out period:
The next time-out period will begin as soon as the watchdog reset has occurred and count down
during the reset sequence. Care must be taken when selecting the PSEL field value so that the
time-out period is greater than the startup time of the chip, otherwise a watchdog reset can reset
the chip before any code has been run.
To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with
the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause
the write operation to be ignored, and the CTRL register value will not change.
The Clear register (CLR) must be written with any value with regular intervals shorter than the
watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start
executing from the boot vector.
When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mode, leaving the WDT operational.
T
Control Register
WDT
Clear Register
Register
= 2
(PSEL+1)
/ f
RC
Register Name
CTRL
CLR
Read/Write
Write-only
Access
AT32UC3B
0x00000000
0x00000000
Reset
85