AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 284

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.9.6
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Transmit Frame Sync Length High Part
• FSEDGE: Transmit Frame Sync Edge Detection
• FSDEN: Transmit Frame Sync Data Enable
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
32059K–03/2011
FSDEN
MSBF
FSEDGE
31
23
15
Others
FSOS
7
-
The four MSB of the FSLEN field.
Determines which edge on Frame Sync will generate the SR.TXSYN interrupt.
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if
TFMR.FSDEN is equal to one.
Note: The four most significant bits for this field are located in the FSLENHI field.
0
1
2
3
4
5
0
1
Transmit Frame Mode Register
Selected Transmit Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
6
-
-
TFMR
Read/Write
0x1C
0x00000000
FSLENHI
DATDEF
FSOS
29
21
13
5
-
28
20
12
4
-
27
19
11
TX_FRAME_SYNC Pin
3
-
Undefined
Input-only
Output
Output
Output
Output
Output
DATLEN
26
18
10
2
-
FSLEN
DATNB
25
17
9
1
-
AT32UC3B
FSEDGE
24
16
8
0
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