AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 331

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.6.8.2
32059K–03/2011
Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous
mode:
In SPI Master Mode:
In SPI Slave Mode:
• the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of
• if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must
• the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the
• to obtain correct behavior of the receiver and the transmitter, the external clock (CLK)
to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK
pin.
must be superior or equal to 4.
be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the
internal clock is selected (CLK_USART).
Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is
provided directly by the signal on the USART CLK pin.
frequency must be at least 4 times lower than the system clock.
See Section “21.6.1.4” on page 304.
However, there are some restrictions:
AT32UC3B
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