AT32UC3B1128-AUT Atmel, AT32UC3B1128-AUT Datasheet - Page 385

• Manufacturer Part Number: AT32UC3B1128-AUT
• Description: IC MCU AVR32 128KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 28
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32059K–03/2011
•Detailed description
TXINI
FIFOCON
Figure 22-18. Example of an IN Endpoint with 2 Data Banks
The data is written, following the next flow:
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on
more details about the KILLBK bit.
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
• The user allows the controller to send the bank and switches to the next bank (if any) by
TXINE is one.
virtual segment (see
481), until all the data frame is written or the bank is full (in which case RWALL is cleared and
the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
clearing FIFOCON.
SW
write data to CPU
BANK 0
Figure 22-19 on page
SW
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
IN
SW
write data to CPU
386. See
BANK 1
(bank 0)
DATA
”Endpoint n Control Register” on page 442
SW
HW
ACK
SW
write data to CPU
IN
BANK0
AT32UC3B
(bank 1)
DATA
to have
ACK
385