HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 21

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTAT
Figure 1.2 Internal Block Diagram of H8/3664N of F-ZTAT
Figure 1.3 Pin Arrangement of H8/3664 of F-ZTAT
Figure 1.4 Pin Arrangement of H8/3664 of F-ZTAT
Figure 1.5 Pin Arrangement of H8/3664 of F-ZTAT
Figure 1.6 Pin Arrangement of H8/3664N of F-ZTAT
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 14
Figure 2.1 Memory Map (2) ......................................................................................................... 15
Figure 2.1 Memory Map (3) ......................................................................................................... 16
Figure 2.2 CPU Registers ............................................................................................................. 17
Figure 2.3 Usage of General Registers ......................................................................................... 18
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 19
Figure 2.5 General Register Data Formats (1).............................................................................. 21
Figure 2.5 General Register Data Formats (2).............................................................................. 22
Figure 2.6 Memory Data Formats................................................................................................. 23
Figure 2.7 Instruction Formats...................................................................................................... 34
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 38
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 41
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 42
Figure 2.11 CPU Operation States................................................................................................ 43
Figure 2.12 State Transitions ........................................................................................................ 44
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 60
Figure 3.2 Stack Status after Exception Handling ........................................................................ 62
Figure 3.3 Interrupt Sequence....................................................................................................... 63
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 65
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 67
(FP-64E, FP-64A)......................................................................................................... 5
(FP-48F, FP-48B) ......................................................................................................... 6
(DS-42S) ....................................................................................................................... 7
(FP-64E) ....................................................................................................................... 8
Same Address ........................................................................................................... 45
Figures
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and Mask-ROM Versions
and Mask-ROM Versions
and Mask-ROM Versions
Version with EEPROM
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Rev. 6.00 Mar. 24, 2006 Page xix of xxviii
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and Mask-ROM Versions ............. 3
Version with EEPROM ............. 4