HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 281

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.4.2
When data is set to ICDR during the period between the execution of an instruction to issue a start
condition and the creation of the start condition, the data may not be output normally, because
there will be a contention between a generation of a start condition and an output of data.
Although data H'FF is to be sent to the ICDR register by a dummy write operation before an issue
of a stop condition, the H'FF data may be output by the dummy write operation if the execution of
the instruction to issue a stop condition is delayed. To prevent these problems, follow the
flowchart shown below during the master transmit operation.
In I
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations synchronize with the ICDR writing are described below.
1. Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
2. Read the BBSY flag in ICCR to confirm that the bus is free.
3. Set bits MST and TRS to 1 in ICCR to select master transmit mode.
4. Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and
5. Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt
6. Write the data (slave address + R/W) to ICDR. With the I
7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has
2
in TSCR, according to the operating mode.
generates the start condition.
request is sent to the CPU.
SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates
the 7-bit slave address and transmit/receive direction. As indicating the end of the transfer, and
so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC continuously not to execute
other interrupt handling routine. If one frame of data has been transmitted before the IRIC
clearing, it can not be determine the end of transmission. The master device sequentially sends
the transmission clock and the data written to ICDR using the timing shown in figure 15.5. The
selected slave device (i.e. the slave device with the matching slave address) drives SDA low at
the 9th transmit clock pulse and returns an acknowledge signal.
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the
transmit operation.
C bus format master transmit mode, the master device outputs the transmit clock and transmit
Master Transmit Operation
2
Rev. 6.00 Mar. 24, 2006 Page 251 of 412
C bus format (when the FS bit in
Section 15 I
2
C Bus Interface (IIC)
REJ09B0142-0600