HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 263

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The I
interface functions. The register configuration that controls the I
Philips configuration, however.
15.1
• Selection of I
• I
• Two ways of setting slave address
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Wait function in master mode
• Wait function in slave mode
• Three interrupt sources
• Selection of 16 internal clocks (in master mode)
• Direct bus drive
 I
 Clocked synchronous serial format: non-addressing format without acknowledge bit, for
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
 Data transfer end (including transmission mode transition with I
 Address match: when any slave address matches or the general call address is received in
 Stop condition detection
 Two pins, SCL and SDA pins function as NMOS open-drain outputs when the bus drive
2
C bus format
2
C bus interface conforms to and provides a subset of the Philips I
master operation only
reception after loss of master arbitration)
slave receive mode
function is selected.
2
C bus format: addressing format with acknowledge bit, for master/slave operation
Features
2
C format or clocked synchronous serial format
Section 15 I
2
C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 233 of 412
2
C bus differs partly from the
Section 15 I
2
2
C bus (inter-IC bus)
C bus format and address
2
C Bus Interface (IIC)
REJ09B0142-0600