HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 232

IC H8 MCU FLASH 32K 64QFP

HD64F3664H

Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3664H

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3664H
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3664H
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3664H H8/3664
Manufacturer:
RENESAS
Quantity:
13
Part Number:
HD64F3664HJ
Manufacturer:
TI
Quantity:
171
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3664HV
Manufacturer:
ALTERA
Quantity:
101
Part Number:
HD64F3664HV
Manufacturer:
RENESAS
Quantity:
630
Part Number:
HD64F3664HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 202 of 412
REJ09B0142-0600
Bit
6
5
4
3
2
1
0
Bit Name
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 14.6, Multiprocessor Communication
Function.
Transmit End Interrupt Enable
When this bit is set to 1, the TEI interrupt request is
enabled.
Clock Enable 0 and 1
Selects the clock source.
Asynchronous mode:
00: Internal baud rate generator
01: Internal baud rate generator
10: External clock
11:Reserved
Clocked synchronous mode:
00: Internal clock (SCK3 pin functions as clock output)
01: Reserved
10: External clock (SCK3 pin functions as clock input)
11: Reserved
Outputs a clock of the same frequency as the bit
rate from the SCK3 pin.
Inputs a clock with a frequency 16 times the bit
rate from the SCK3 pin.

Related parts for HD64F3664H