HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 249

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.5.3
Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
7. The SCK3 pin is fixed high.
Figure 14.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
TDRE
TEND
LSI
operation
User
processing
been written to TDR, and transfers the data from TDR to TSR.
this time, a transmit data empty interrupt (TXI) is generated.
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD
pin.
of the next frame is started.
Serial
clock
Serial
data
the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
Serial Data Transmission
TXI interrupt
request
generated
Bit 0
Bit 1
TDRE flag
cleared to 0
Data written
to TDR
1 frame
TXI interrupt request generated
Bit 7
Bit 0
Section 14 Serial Communication Interface 3 (SCI3)
Bit 1
Rev. 6.00 Mar. 24, 2006 Page 219 of 412
1 frame
Bit 6
TEI interrupt request
generated
REJ09B0142-0600
Bit 7