HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 231

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.6
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Bit
3
2
1
0
Bit
7
Serial Control Register 3 (SCR3)
Bit Name
STOP
MP
CKS1
CKS0
Bit Name
TIE
Initial
Value
0
0
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit
is 0, it is treated as the start bit of the next transmit
character.
Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
PM bit settings are invalid. In clocked synchronous
mode, this bit should be cleared to 0.
Clock Select 0 and 1
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register
setting and the baud rate, see section 14.3.8, Bit Rate
Register (BRR). n is the decimal representation of the
value of n in BRR (see section 14.3.8, Bit Rate
Register (BRR)).
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 201 of 412
REJ09B0142-0600