HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 72

IC H8 MCU FLASH 32K 64QFP

HD64F3664H

Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3664H

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3664H
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3664H
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3664H H8/3664
Manufacturer:
RENESAS
Quantity:
13
Part Number:
HD64F3664HJ
Manufacturer:
TI
Quantity:
171
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3664HV
Manufacturer:
ALTERA
Quantity:
101
Part Number:
HD64F3664HV
Manufacturer:
RENESAS
Quantity:
630
Part Number:
HD64F3664HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 2 CPU
2.6.2
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 19.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, access is completed in two cycles. In two-state access, the operation timing
is the same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Rev. 6.00 Mar. 24, 2006 Page 42 of 412
REJ09B0142-0600
On-Chip Peripheral Modules
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
or
SUB
T
1
state
Address
Bus cycle
T
2
state
Read data
Write data
T
3
state

Related parts for HD64F3664H