HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 43

• Manufacturer Part Number: HD64F3664H
• Description: IC H8 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664H

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
• Upward-compatible with H8/300 CPUs
• General-register architecture
• Sixty-two basic instructions
• Eight addressing modes
• 64-kbyte address space
• High-speed operation
• Power-down state
 Can execute H8/300 CPUs object programs
 Additional eight 16-bit extended registers
 32-bit transfer and arithmetic and logic instructions are added
 Signed multiply and divide instructions are added.
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
 8/16/32-bit data transfer and arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract
 8 × 8-bit register-register multiply
 16 ÷ 8-bit register-register divide
 16 × 16-bit register-register multiply
 32 ÷ 16-bit register-register divide
 Transition to power-down state by SLEEP instruction
Section 2 CPU
: 2 state
: 14 states
: 14 states
: 22 states
: 22 states
Rev. 6.00 Mar. 24, 2006 Page 13 of 412
REJ09B0142-0600
Section 2 CPU